/*-----------------------------------------------------------------------
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							   \\  - -  //
								(  @ @  )
+-----------------------------oOOo-(_)-oOOo-----------------------------+
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2013-20xx CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
Email Address 		: 		thereturnofbingo@gmail.com
Filename			:		PC2FPGA_UART_Test.v
Data				:		2013-10-31
Description			:		Test UART Communication between PC and FPGA.
Modification History	:
Data			By			Version			Change Description
=========================================================================
13/10/31		CrazyBingo	1.0				Original
-------------------------------------------------------------------------
|                                     Oooo								|
+------------------------------oooO--(   )-----------------------------+
                              (   )   ) /
                               \ (   (_/
                                \_)
----------------------------------------------------------------------*/   

`timescale 1ns/1ns
module PC2FPGA_UART_Test
(
	//global clock 50MHz
	input				clk,			//50MHz
	input				rst_n,			//global reset
	
	//user interface
	input				fpga_rxd,		//pc 2 fpga uart receiver
	output				fpga_txd,		//fpga 2 pc uart transfer
	output				divide_clk,		//precise clock output

	//74595 led interface
	output				led595_dout,	//74hc595 serial data input	
	output				led595_clk,		//74hc595 shift clock (rising edge)
	output				led595_latch	//74hc595 latch clock (rising edge)		
);

//----------------------------------
//sync global clock and reset signal
wire	clk_ref;
wire	sys_rst_n;
system_ctrl_pll	u_system_ctrl_pll
(
	.clk			(clk),			//50MHz
	.rst_n			(rst_n),		//global reset

	.clk_c0			(clk_ref),		//100MHz	
	.sys_rst_n		(sys_rst_n)		//system reset
);



//------------------------------------
//Precise clk divider
wire	divide_clken;
precise_divider	
#(
	//DEVIDE_CNT = 42.94967296 * fo
	
//	.DEVIDE_CNT	(32'd175921860)	//256000bps * 16	
//	.DEVIDE_CNT	(32'd87960930)	//128000bps * 16
//	.DEVIDE_CNT	(32'd79164837)	//115200bps * 16
	.DEVIDE_CNT	(32'd6597070)	//9600bps * 16
)
u_precise_divider
(
	//global
	.clk				(clk_ref),		//100MHz clock
	.rst_n				(sys_rst_n),    //global reset
	
	//user interface
	.divide_clk			(divide_clk),
	.divide_clken		(divide_clken)
);



wire	clken_16bps = divide_clken;
//---------------------------------
//Data receive for PC to FPGA.
wire			rxd_flag;
wire	[7:0]	rxd_data;
uart_receiver	u_uart_receiver
(
	//gobal clock
	.clk			(clk_ref),
	.rst_n			(sys_rst_n),
	
	//uart interface
	.clken_16bps	(clken_16bps),	//clk_bps * 16
	.rxd			(fpga_rxd),		//uart txd interface
	
	//user interface
	.rxd_data		(rxd_data),		//uart data receive
	.rxd_flag		(rxd_flag)  	//uart data receive done
);

//---------------------------------
//Data receive for PC to FPGA.
uart_transfer	u_uart_transfer
(
	//gobal clock
	.clk			(clk_ref),
	.rst_n			(sys_rst_n),
	
	//uaer interface
	.clken_16bps	(clken_16bps),	//clk_bps * 16
	.txd			(fpga_txd),  	//uart txd interface
           
	//user interface   
	.txd_en			(rxd_flag),		//uart data transfer enable
	.txd_data		(rxd_data), 	//uart transfer data	
	.txd_flag		() 			//uart data transfer done
);




//---------------------------
//The driver of 74HC595
led_74595_driver	u_led_74595_driver
(
	//global clock
	.clk				(clk),
	.rst_n				(rst_n),

	//74hc595 interface
	.led595_dout		(led595_dout),	//74hc595 serial data input	
	.led595_clk			(led595_clk),	//74hc595 shift clock (rising edge)
	.led595_latch		(led595_latch),	//74hc595 latch clock (rising edge)

	//user interface
	.led_data			(rxd_data)		//led data input	
);

endmodule

